The present invention relates generally to signal processing apparatus and more particularly to a programmable charge domain device which allows a sampled analog signal to be multiplied by a multiple-bit digital word coefficient.
A new class of integrated circuits, called charge domain devices (CDD) has been developed with the goal of performing signal processing functions with accuracy and speed performance exceeding alternative technologies. The starting point for this development is conventional charge transfer device (CTD) technology. Devices of this type, such as charge coupled device (CCD) transversal filters, have been demonstrated in many cases, particularly at high frequencies, to be more efficient in performing certain sampled data processing functions than such alternative techniques as digital filters or switched capacitor devices. However, as the speed and accuracy performance requirements increase, conventional CTD's also encounter a number of limitations. In order to understand the origin of some of these limitations, the operation of conventional CTDs is described briefly herein.
Conventional CTD's derive their output signal by sensing charge packets with overlying MOS electrodes. Multiplication of these charges by tap weights is implemented by splitting the overlying electrodes in proportion to the desired impulse response coefficient, and summation is implemented by connecting the overlying electrodes. This implementation is particularly efficient, since all of the mathematical operations required for a particular filter response are accomplished automatically by simple physical laws rather than by manipulating binary bits in complex logic circuits, but it creates at least two problems. First, as the specifications on the system increase, and the number of filter coefficients needed to accomplish the desired transfer function increases, the total capacitance of the output electrode increases, making high speed operation more difficult; and second, non-linearities in the relationship between the charge in the packets and the voltage induced on the overlying electrodes usually compromises the accuracy of the transfer function if buried channel technology is used. These constraints have in the past limited the frequency handling capabilities of conventional CTD filters to a few megahertz.
Charge domain integrated circuits have been developed to overcome these limitations so, as to increase the frequency range that can be handled by monolithic signal processing chips. In charge domain devices, all signal processing is performed by manipulating the charge packets themselves, rather than using the image charge on overlying electrodes. The charge packets representing the input signal may be split, routed, delayed and combined to form new charge packets that represent the output signal. But since the splitting and routing depend only on the plan view geometry of the devices that accomplish it, and not on the details of the capacitance-voltage characteristic, buried channel technology can be used without degrading the accuracy of the transfer function. Furthermore, since portions of some charge packets can be routed backwards in the signal flow sense and re-introduced into the forward path, CDD's, yield the new possibility of filters with infinite impulse response; i.e., filters that implement poles as well as zeroes in their transfer function. Finally, since the output of these devices is a stream of charge packets, low capacitance diode sensing of the charge is used to generate the output signal. Thus, the output capacitance does not increase as the filter architecture becomes more complex, and device speed is limited only by the speed of charge transfer which, for buried channel technology, may be as fast as hundreds of megahertz.
Conventional CCD transversal filters use fixed tap weights which are determined photolithographically. This means that an entirely new device must be fabricated for each new application.
Many new approaches have been proposed for making CTD filters programmable, but all of these have serious drawbacks. One approach uses MNOS transistors as the multipliers for each coefficient, but these are difficult to process reliably and the accuracy and lifetimes are limited. In another approach, MOS switches are used to connect the overlying electrodes to the plus or minus terminals of a differential amplifier providing coefficients of plus or minus one. Arbitrary coefficients can be obtained by paralleling filters with binary weightings and summing the outputs, but this requires N channels for N bit coefficients which uses up area and power. Also, threshold variations between channels causes accuracy degradation.